Efficient soft core multiplier for post quantum digital signatures

Shah, Yasir Ali, Rafferty, Ciara, Khalid, Ayesha, Khan, Safiullah ORCID: https://orcid.org/0000-0001-8342-6928, Javeed, Khalid and O'Neill, Máire (2024) Efficient soft core multiplier for post quantum digital signatures. In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 19 May 2024 - 22 May 2024, Singapore.

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Abstract

Multiplication is a core operation in various applications such as cryptography and machine learning. Dedicated DSP blocks are provided by FPGA vendors for multiplication. However, these DSP blocks are limited in number and their location on FPGA is fixed, resulting in routing delays that affects the performance for small size multipliers. In this paper, a high performance and resource efficient 5 × 5 multiplier is presented that utilizes lookup tables (LUTs) and fast carry chain of the FPGA. The proposed multiplier offers 30% reduction in LUTs compared to Vivado DSP-less inferred multiplier at the cost of a slight increase in critical path delay (CPD). The proposed multiplier requires lesser power consumption and has better area- delay product (ADP) and power-delay product (PDP) metrics. Based on the proposed multiplier, a finite field multiplier is developed for post quantum digital signatures such as QR-UOV, MAYO and MQOM. The matrix-vector architecture is the core operation in multivariate digital signatures and integration of our finite field multiplier in a matrix-vector architecture shows that area is almost halved compared to state-of-the-art.