Tanlock based loop with improved performance

Al-Ali, Omar Alkharji (2012) Tanlock based loop with improved performance. Doctoral thesis (PhD), Manchester Metropolitan University.

Preview

Available under License Creative Commons Attribution Non-commercial No Derivatives. Download (788kB) | Preview

Abstract

This thesis is focused on the design, analysis, simulation and implementation of new improved architectures of the Time Delay Digital Tanlock Loop (TDTL) based digital phase-locked loop (DPLL). The proposed architectures overcome some fundamental limitations exhibited by the original TDTL. These limitations include the presence of nonlinearity in the phase detector (PD), the non-zero phase error of the first-order loop, the restricted locking range, particularly of the second-order loop, the limited acquisition speed and the noise performance. Two approaches were adopted in this work to alleviate these limitations: the first involved modifying the original TDTL through the incorporation of auxiliary circuit blocks that enhance its performance, whilst the second involved designing new tanlock-based architectures. The proposed architectures, which resulted from the above approaches, were tested under various input signal conditions and their performance was compared with the original TDTL. The proposed architectures demonstrated an improvement of up to fourfold in terms of the acquisition times, twofold in noise performance and a marked enhancement in the linearity and in the locking range. The effectiveness of the proposed tanlock-based architectures was also assessed and demonstrated by using them in various applications, which included FM demodulation, FM threshold extension, FM demodulation with improved THD (total harmonic distortion), and Doppler effect improvement. The results from these applications showed that the performance of the new architectures outperformed the original TDTL. Real-time performance of these architectures was evaluated through implementation of some of them on an FPGA (field-programmable gate array) based system. Practical results from the prototype FPGA based implementations confirmed the simulation results obtained from MATLAB/Simulink.